1. Field of the Invention
The present invention relates to charge pump circuits having leakage elements arranged to act as protective shunt elements across low-voltage semiconductor devices, and in particular, but not exclusively, to such circuits having high impedance diodes with current leakage characteristics.
2. Description of the Related Art
Capacitive charge pumps and their use in generating higher voltages from a lower-voltage power supply are well known. Their use is increasing due to the proliferation of battery-powered consumer gadgets such as MP3 players and mobile phones. For example one use is to provide a voltage for MEMS microphone transducers, where a 12V transducer bias voltage may need to be derived from a supply as low as 1.5V.
FIG. 1a illustrates a general capacitive charge pump comprising four pumped capacitors C1 to C4 interposed between switching stages SS1 to SS4. In operation, the voltages on the bottom plates of C1 to C4 are pulsed between an input voltage Vin and ground in alternate clock phases. The top plate of each capacitor is also connected to the top plate of an adjacent capacitor via a switching stage SS2-4. The first capacitor in the chain is also linked via switching stage SS1 to another voltage signal which is also conveniently equal to Vin. Each capacitor top plate cycles between a respective pair of voltages, with these voltages increasing along the chain, in this case delivering an output voltage of 6V to the last, unswitched, capacitor C4.
The switch elements may be simple diodes, as in the well known Dickson charge pump, but for higher efficiency and a more accurate output voltage they may be MOS switch transistors, driven, via level shift circuits LS1 to LS4 by another set of clock pulses to connect adjacent pairs of capacitors together in alternate clock phases.
FIG. 1b illustrates the voltage levels at the nodes of the switching stages with the solid and dashed lines indicating the voltage levels achieved during different stages of the clock cycle. Thus the voltage at Vin is constant. However the voltage at V2 alternates between Vin and 2Vin. Similarly the voltage at V3 varies between 2Vin as a low voltage and 3Vin as a high voltage, but with the pattern of high and low voltage being of opposite phase to that at node V2. It can be seen from FIG. 1b that the voltage difference across each switch element when off never exceeds twice the input voltage Vin. It is thus possible to construct such a charge pump using devices designed only to operate with up to 2.Vin across them. This has advantages in that these devices are smaller than higher voltage devices, so occupy less chip area and need less charge to turn on and off each clock cycle. In many applications, such as the above-mentioned MEMS microphone transducer application, other electronics present in the device do not require high-voltage transistors, so a simpler cheaper silicon fabrication process with only low-voltage transistors can be used in manufacture.
Using low-voltage transistors as the switches does require some extra circuitry to shift the voltage levels of the driving switch waveforms from near ground to near the increasing voltage levels of each stage, possibly using more switched capacitors to level-shift these voltages. However such circuitry is relatively simple.
In steady state, the voltage waveforms in each part of the circuit and across each transistor are predictable, and excessive voltages can be avoided by appropriate design.
However in other scenarios, for example in power-down, it is hard to predict all possible power-down transients, as these will depend on the timing and the speed of the powering down of the supply, and the output of any clock waveform generator in all possible cases. If the supply disappears suddenly, the switches may find themselves stuck in one phase, or possibly all turned off. In such a case, at least some of the capacitors may be at high voltages, and only decay to ground gradually via small leakage currents associated with junctions to which they are connected. But processing variations across a circuit, or differences in circuit design at different nodes may result in some node voltages decaying faster than others. For example the final capacitor is often much larger than the others to reduce ripple on Vout, so this may decay more slowly, unless the applied load is still taking current. This is illustrated in FIG. 1c, which shows the voltage levels at one clock phase (solid line) and the voltage decay a certain time later (dot-dash line). In this example C3 is shown as decaying to ground much quicker than C4, perhaps also due to a minor defect in a junction coupled to C3 increasing its leakage to ground. In this example a large voltage develops between C3 and C4, across switch block SS4.
Such a large voltage may damage constituent elements of SS4, for instance the voltage may be above the breakdown voltage of any transistor elements and exceeding the breakdown voltage may stress the transistors to breaking point, especially if repeated often. Such power cycling is becoming more prevalent as more complex power management schemes are employed in portable equipment to reduce power consumption. Also as silicon technology evolves to use smaller transistors economically, there is generally less safety margin possible, so the transistors are more fragile than in older technologies.
Similar issues of possible high voltages may arise not only across the switch elements, but also in the capacitor level-shifting circuits LS1 to LS4. Internal voltages in such circuits may not be predictable in power down scenarios and again large voltages may lead to lifespan reduction or failure.
Further if the device does not power down properly, there may be peculiar transients on power-up which could again cause damage to the device.
There is thus a requirement for some means of ensuring that excessive voltages do not develop across low-voltage elements in these charge pumps, especially at nodes that are capacitively pumped and so may not always be directly driven high or low, and may be at high voltages before power down.
It is therefore an aim of the present invention to provide a charge pump circuit which mitigates at least some of the aforementioned disadvantages.